1. Field of the Invention
This invention relates to non-volatile memory architectures and methods for simultaneously erasing memory cells in a memory array while reading or writing other memory cells in the same memory array.
2. Description of Related Art
A conventional erasable non-volatile semiconductor memory includes an array of memory cells arranged in rows and columns. Each memory cell typically includes a memory transistor, such as floating or split gate transistor, having a control gate coupled to an associated row (or word) line in the array, a drain coupled to an associated column (or bit) line in the array, and a source coupled to associated source line in the array. Each memory cell may also include a select transistor located between the drain or source of a floating gate transistor and the associated column or source line. A threshold voltage of the memory transistor represents stored information. Typically, to write data in memory cells, the memory cells are first erased to set the threshold voltage of the memory transistor in an erased state, for example, a low (or a high) threshold voltage level. Data are then written to the memory cells by programming selected cells to raise (or lower) the threshold voltage of the memory transistor.
A Flash memory simultaneously erases all memory cells in a sector of a memory array. A sector is defined as a group of memory cells which share a common erase/source line. One conventional erase process grounds the row lines in the memory array (xe2x80x9cgrounded-gate erasexe2x80x9d scheme), allows the column lines in the array to float, and applies an erase voltage (typically about 12 volts) to the source line or lines coupled to the sector being erased. Another known erase process applies a negative voltage (typically about xe2x88x9210 volts) to the row line or lines coupled to the memory cells in the sector being erased (xe2x80x9cnegative-gate erasexe2x80x9d scheme), allows the column lines in the array to float, and applies a lower positive erase voltage (typically about 5 volts) to the source line or lines coupled to memory cells in the sector being erased. These erase processes rely on Fowler-Nordheim tunneling to reduce the negative charge on floating gates of the memory transistors being erased and thereby lower the threshold voltages of the erased memory transistors. Erase processes using Fowler-Nordheim tunneling are relatively slow.
In a single array, erase processes usually cannot be simultaneous with write or read processes because write and read processes require bias conditions on row (or gate), column, and source that differ from bias conditions used for an erase process. For example, EPROMs and Flash EPROMs conventionally use a write process that relies on channel hot electron (CHE) injection to increase the threshold voltage of a selected memory transistor. Table 1 below lists typical bias conditions for erase, write, and read processes. The write process is for a typical CHE process, which creates in the selected memory transistor a current that injects channel hot electrons into the floating gate of the memory transistor and increases the threshold voltage of the memory transistor to a desired value. The erase process lists conditions for both the erase processes mentioned above, i.e., the grounded-gate scheme and negative-gate erase scheme. The voltage applied to the gate or row line associated with the selected memory transistor is Vg, the voltage applied to the drain or column line associated with the selected memory transistor is Vd, and the voltage applied to the source or source line associated with the selected memory transistor is Vs.
Certain applications of non-volatile memory would benefit from the ability to simultaneously perform erase and write or read operations. For example, analog Flash memory can record continuous analog signals such as sound or voice signals and may require erasing sectors of the flash memory during the recording to provide storage to maintain a continuous recording process. U.S. patent application Ser. No. 08/839,288, now U.S. Pat. No. 5,949,716, entitled xe2x80x9cLook-Ahead Erase For Sequential Data Storage,xe2x80x9d which is hereby incorporated by reference herein in its entirety, describes structures and methods that simultaneous erase a sector in one memory array while writing to a sector in another memory array. These memories employ multiple array architectures which may be more costly and require more overhead and complexity than conventional single array architectures. For digital applications, conventional or multi-bit-per-cell storage, simultaneous erase and write/read capabilities offer significant cost savings to the system designer. In addition to Flash memory, many of today""s embedded systems contain additional memory devices such as EEPROM or SRAM devices. Previously, these separate devices were required to store parameter/configuration code and/or user specification data. Furthermore, a separate memory device was required to run the Flash memory program and write algorithms. By eliminating the need for these devices, lower system level costs and simpler memory designs are possible.
In accordance with the invention, a memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. In one embodiment, the memory is a Flash memory having a row based sector architecture, i.e., sectors that contain one or more complete rows of memory cells. During an erase operation, an erase voltage applied to the source lines for one or more rows corresponding to a sector does not affect write or read operations being performed in other sectors, i.e., other rows. Similarly, voltages applied to row lines for access to a memory cell have no effect on the erase operation being performed in another sector because no memory cell experiences both the erase voltage applied to source lines and the access voltage applied to row lines for access. The column line voltage applied for access to a memory cell could affect the erase operation since column lines cross the erased sector. However, if a positive voltage is applied to the column lines for access to the memory cell, that voltage has little effect on the erase process since a floating drain commonly has a positive voltage for a typical erase operation. Additionally, the memory cells in the sector being erased do not conduct or significantly change the voltages on column lines or disturb memory cell accessed for a read or write operation.